Cadence has expanded its ChipStack AI Super Agent with a new RTL Generation Agent designed to turn natural-language chip specifications into optimized register-transfer-level code.

The tool automates specification-to-RTL generation, RTL analysis and refinement while targeting power, performance and area (PPA). It also uses Cadence’s established electronic design automation tools to analyze and verify the generated design rather than relying on a foundation model alone.

In early evaluations, Cadence says the agent produced RTL with an average 24% reduction in area and 18% reduction in power compared with pure foundation-model code generation while maintaining functional accuracy in those evaluations. Those figures are Cadence’s early results, not a comparison against expert human-written RTL.

The agent can also modify existing RTL. Engineers can describe new architecture, functionality or PPA requirements at a high level, and the workflow updates the design while checking the resulting functionality and physical targets.

Honda R&D is evaluating the technology for advanced automotive system-on-chip designs. Cadence says the expanded ChipStack capabilities are expected to reach select early-access customers in the fourth quarter of 2026.

The development shows AI moving deeper into the semiconductor engineering workflow, from assisting verification toward generating portions of the design itself. BitcoinVersus.tech’s coverage of the TSMC advanced packaging hub examines another part of the increasingly automated chip-development and manufacturing pipeline.

Read Cadence’s announcement of the RTL Generation Agent for the complete technical description and availability information.

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