Cadence and TSMC are pushing AI chip design beyond the boundaries of a single die. Their expanded collaboration combines certified A14 design flows, UALink connectivity, new N3P and N2P IP, and TSMC 3DFabric support for wafer-scale systems containing hundreds of chiplets.
In its September 23 announcement, Cadence said its digital, signoff, custom and analog flows are now certified for TSMC A14, while its broader collaboration spans N3, N2, A16 and A14. The same program also extends into 3D-IC design, high-speed interface IP and agentic AI workflows.
A14 is becoming a full design ecosystem, not just a node
A process node only becomes commercially useful when designers can reliably build, verify and sign off chips for it. Cadence says its A14 support now includes implementation, timing, power, extraction, custom/analog design and physical verification flows rather than a single point tool.
That matters because the complexity of advanced-node AI chips is increasingly shifting from transistor scaling alone toward system-level co-design. BitcoinVersus.Tech recently covered how Synopsys and TSMC are bringing agentic AI into A14 design. Cadence is attacking the same complexity from its own toolchain while adding interconnect and multi-die design support.
A semiconductor industry post on X highlighted the same combination: A14 certification, N3P/N2P IP, wafer-scale 3D-IC support and agentic AI flows.
UALink moves the scale-up network onto the semiconductor roadmap
The UALink portion of the announcement is especially important for AI accelerators. UALink is designed as a high-speed scale-up interconnect for connecting accelerators inside tightly coupled AI systems. Cadence says it has demonstrated a UALink solution on TSMC N3P, bringing the interconnect closer to the same silicon-design ecosystem used for advanced compute dies.
That creates a direct bridge between chip design and AI-system networking. Instead of treating the accelerator and its scale-up fabric as separate engineering problems, designers can increasingly plan compute, SerDes, packaging and interconnect together.
Converge Digest reported that the collaboration also extends into 224G SerDes integration and wafer-scale systems with hundreds of chiplets, reinforcing how quickly AI networking is moving into package-level and die-level architecture.
Hundreds of chiplets changes what “a chip” means
TSMC 3DFabric support for wafer-scale systems containing hundreds of chiplets is not the same as announcing a specific production processor with hundreds of dies. It is design enablement: the software, verification, packaging and interface infrastructure needed to make architectures at that scale possible.
BitcoinVersus.Tech has already examined one reason the industry is moving in this direction. CoWoS-L is pushing AI packages beyond conventional reticle limits, allowing compute and memory systems to grow by combining multiple dies and advanced interposers rather than relying on one monolithic piece of silicon.
As packages grow, the engineering burden shifts. Power delivery, thermal gradients, signal integrity, mechanical stress, clocking and die-to-die latency all become system-level constraints. EDA software has to understand those interactions before a design reaches manufacturing.
UCIe-64G and LPDDR6 fill in the chiplet plumbing
Cadence also says its UCIe-64G IP has taped out on TSMC A14, while LPDDR6 IP is in development. UCIe targets standardized die-to-die communication inside chiplet packages, while LPDDR6 expands the memory-interface roadmap for systems that need high bandwidth without the cost structure of HBM everywhere.
The result is a more complete platform: leading-edge compute on A14, chiplet links through UCIe, accelerator-scale connectivity through UALink, advanced packaging through 3DFabric and a growing set of memory and networking interfaces around them.
AI is also moving into the EDA workflow itself
Cadence is pairing the physical technology with AI-assisted design. BitcoinVersus.Tech recently covered Cadence adding an AI agent for RTL chip design. The TSMC partnership extends that direction into advanced-node implementation and 3D-IC workflows, where designers face too many interacting constraints for purely manual iteration to scale efficiently.
Cadence says automated migration in its Virtuoso environment can reduce layout iterations by as much as 2.5× for A16 and A14 work. That does not mean AI has replaced chip engineers. It means the optimization loop—place, route, verify, analyze, revise—is becoming increasingly software-driven and agent-assisted.
The semiconductor race is becoming a systems race
The broader message is that the next generation of AI hardware will not be defined by transistor density alone. Competitive systems increasingly depend on the interaction between process technology, chiplets, packaging, memory, scale-up links, optical and electrical I/O, power delivery and the software used to design all of it.
Cadence and TSMC are building infrastructure for that transition. A14 shrinks the transistors. UCIe and UALink connect the pieces. 3DFabric expands the package. Agentic EDA tries to keep the resulting design complexity manageable. The interesting benchmark will be which production AI systems can turn that stack into better performance per watt and faster time to silicon.
BitcoinVersus.Tech
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