Everspin Technologies has demonstrated what it calls the first CXL-connected MRAM platform, placing persistent memory directly on the Compute Express Link fabric for AI and data-center workloads. In the company’s September 29 announcement, the working system combines PERSYST MRAM with a CXL-enabled server to create a memory-semantic tier between volatile DRAM and NAND storage.

The demonstration matters because AI infrastructure increasingly runs into a memory problem as well as a compute problem. Processors and accelerators can sit idle while data moves between memory and storage tiers. Everspin’s approach is designed to keep frequently written or restart-sensitive data closer to the processor while retaining it through power loss.

A persistent tier between DRAM and NAND

MRAM, or magnetoresistive random-access memory, stores data using magnetic states rather than the charge-based storage used by conventional DRAM. The important operational difference is persistence: MRAM can retain data without power while still behaving much more like memory than a conventional SSD.

Everspin says its CXL demonstration provides cache-line-level, nanosecond-class access and writes up to 100 times faster than NAND-based solid-state storage. That 100× figure is a company performance claim from the demonstrated platform, not an independently reproduced BitcoinVersus.tech benchmark.

The architecture complements the broader CXL transition BitcoinVersus.tech recently examined with Astera Labs’ Leo X-Series CXL 3.2 memory controllers. CXL is increasingly being used to separate memory capacity from a single processor socket and make that capacity available as a pooled system resource.

The demo used real server hardware

The test platform used a Supermicro AS-1116CS-TN server with a 32-core AMD EPYC 9355 processor, an AMD Alveo U250 FPGA carrying a Wolley CXL controller, and Everspin PERSYST 1GB DDR4 MRAM UDIMMs. Everspin and Wolley demonstrated reads and writes through the CXL interface under test conditions at SNIA Developer Conference 2026.

The surrounding technical program supports the significance of the experiment. The conference agenda included dedicated sessions on MRAM, CXL fabric management, shared KV caches across GPUs and persistent KV caching, showing how memory fabrics and AI inference are converging as one systems problem.

Everspin CEO Sanjeev Aggarwal explains MRAM’s persistence, performance characteristics and AI use cases in this English-language Future Tech Investor Conference interview hosted by RedChip.

AI checkpointing and KV cache are the practical targets

Two AI workloads stand out. The first is checkpointing, where a running model periodically saves state so a failure does not force a long computation to restart from the beginning. Persistent memory can reduce the amount of state that must be flushed down to slower storage.

The second is key-value cache for large-language-model inference. KV cache grows as conversations and context windows grow, making memory capacity and data movement important constraints on inference. BitcoinVersus.tech has separately tracked the expansion of AI memory beyond HBM as vendors attack different points in that hierarchy.

Unlike HBM attached directly to an accelerator, CXL-connected persistent memory would occupy a different performance and capacity tier. The engineering question is therefore not whether MRAM replaces every memory technology, but whether its combination of persistence, latency and endurance is valuable enough for specific data structures to justify its cost.

What still needs to be proven

A conference demonstration is not a production deployment. Customer workload testing still needs to establish application-level latency, throughput, endurance, capacity economics, controller overhead and the software changes required to use the tier efficiently.

Capacity is another key issue. Modern AI systems operate at scales far beyond the 1GB modules used in the demonstration. The value of CXL-connected MRAM will therefore depend on how the technology scales in density and cost while preserving its latency and persistence advantages.

Those questions fit a broader trend visible in Micron’s 512GB DDR5 server-memory demonstration: AI infrastructure is forcing designers to reconsider not just accelerator throughput but the entire path data takes through a server.

Everspin’s result is therefore best read as a systems milestone. CXL gives persistent MRAM a standards-based route into modern servers; the next step is proving that the additional tier delivers enough real workload benefit to become part of production AI infrastructure.

BitcoinVersus.Tech

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