Credo is using AMD Versal programmable hardware to demonstrate a new way to give AI accelerators much larger memory pools without waiting for a custom chip.
On October 13, 2026, Credo announced that it is showing its OmniConnect Weaver memory fanout gearbox running on an AMD Versal AI Edge Series Gen 2 adaptive SoC evaluation board at the OCP Global Summit in San Jose. The company says the setup can expose terabyte-class LPDDR memory capacity to a programmable-logic XPU over VSR links.
The idea targets a basic AI infrastructure problem: accelerator compute has grown faster than the memory systems feeding it. BitcoinVersus.Tech recently covered SK hynix expanding AI memory beyond HBM, another sign that capacity, bandwidth and memory placement are becoming first-class design problems rather than background specifications.
Credo says OmniConnect separates memory from the accelerator package and connects larger LPDDR pools through its Weaver gearbox. In the demonstrated architecture, the expanded memory is transparent above the controller, meaning application software does not need to be rewritten simply to see the larger capacity. Credo also says the design uses standard organic packaging rather than a silicon interposer.
Credo has been positioning OmniConnect as part of a broader effort to standardize lightweight memory and chip-to-chip links for AI systems.
AMD’s role is important because Versal is programmable after deployment. That gives system builders a platform for testing new memory architectures before committing to a fixed ASIC. BitcoinVersus.Tech has also followed AMD’s use of UCIe links in Versal RF, which reflects the same broader movement toward modular compute, memory and I/O.
AMD’s official VEK385 overview shows the Versal AI Edge Series Gen 2 evaluation platform used for programmable system development.
The comparison with conventional accelerator memory is straightforward. HBM delivers extremely high bandwidth close to the compute die, but capacity is constrained by packaging, cost and physical integration. LPDDR can offer much larger pools at lower cost, although the architecture must solve the latency and bandwidth penalties created by moving memory farther away.
AMD has already been experimenting with different memory arrangements. Its Versal AI Core work for long-life systems shows why programmable hardware can matter when designers need architectures that remain useful across long product cycles.
There is still an important limitation: Credo’s announcement describes a working demonstration, not independently benchmarked production performance. The company has not published enough application-level data to show how much the larger memory pool improves real inference throughput, latency or power efficiency compared with HBM-based systems.
Even so, the demonstration is notable because it turns memory expansion into something system designers can test on programmable hardware today. If the approach scales cleanly, AI accelerators may have more options between tightly integrated HBM and slower conventional host memory.
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