A new class of Ethernet switch processors is doubling the bandwidth available on a single chip in 2026, as Broadcom, Cisco, NVIDIA and Marvell compete for the networking equipment connecting the world’s largest AI clusters. The leading designs advertise 102.4 terabits per second (Tbps) of aggregate switching capacity, versus 51.2 Tbps for the prior generation. But the products are not equally mature: some are already shipping in volume, while others have entered sampling or remain scheduled for release.

This countdown compares seven named Ethernet switching ASICs by manufacturers’ advertised per-chip capacity, as documented through October 30, 2026. It includes announced silicon but flags availability; ties are grouped by capacity and numbered for editorial presentation, not as proof of faster performance within a tie. Larger multi-chip switch systems, router-only processors and proposed 200T–400T designs without a comparable shipped or sampled 2026 chip are outside the comparison.

A switch’s bandwidth rating represents the amount of traffic its switching fabric is designed to handle, not the speed of one network cable. For example, 64 ports at 1.6 Tbps total 102.4 Tbps; an alternative arrangement could use 128 ports at 800 Gbps. Port availability, oversubscription, packet sizes and application behavior determine what happens in a live network.

7. Broadcom Tomahawk 5 — 51.2 Tbps

Broadcom’s BCM78900 Tomahawk 5 made 51.2 Tbps mainstream for high-density Ethernet switching. It can support up to 64 × 800GbE, 128 × 400GbE or 256 × 200GbE connections in different configurations, all sharing the same total switch bandwidth. Broadcom announced volume production in March 2023, making this one of the established shipping options entering 2026.

Tomahawk 5 also brought adaptive routing, congestion control and packet-buffer features to AI and cloud networks. It remains relevant in equipment where 800GbE links and an installed software ecosystem matter more than being on the newest silicon generation. The company’s successor, Tomahawk 6, doubles the published capacity.

6. Marvell Teralynx 10 — 51.2 Tbps

The Marvell Teralynx 10 also delivers 51.2 Tbps, with low-latency packet forwarding and a programmable pipeline intended for hyperscale networks. Marvell confirmed volume production and customer deployments in July 2024, citing packet latency as low as 500 nanoseconds under its stated test conditions and support for open switching software such as SONiC.

ServeTheHome examines a real 64-port, 800GbE Teralynx 10-based switch, including the ASIC, optics and cooling.

A 64-port 800GbE switch demonstrates how the capacity rating translates into physical interfaces, while also revealing the practical thermal budget: pluggable optics and high-performance silicon can together draw substantial power. The video is a look at shipping-class hardware rather than a conceptual rendering.

5. Cisco Silicon One G302 — 51.2 Tbps

Cisco introduced its Silicon One G302 at the October 12 Open Compute Project summit. The new 51.2-Tbps ASIC is geared toward top-of-rack switches with 200G-class serializer/deserializer interfaces, 1.6TbE ports and direct-to-chip cooling options. Its 256 high-speed SerDes lanes distinguish its electrical interface design from earlier 51.2-Tbps products.

Cisco describes the Silicon One architecture underlying its data-center switch portfolio, including the G-Series relevant to the new G302.

The G302 had not been confirmed as shipping by October 30: Cisco planned to begin customer shipments before the end of 2026. In this ranking it represents a newly announced chip at the 51.2-Tbps tier, not an installed product with verified production deployments. Our earlier G302 report covers the top-of-rack design in greater detail.

4. Marvell Teralynx T100 — 102.4 Tbps

Marvell’s new Teralynx T100 joins the higher tier with 102.4 Tbps in a design produced on 3-nanometer technology. The manufacturer says it targets under 1,000 watts of typical switch-chip power and up to a 25% power reduction versus the competitive systems in its comparison. Those efficiency figures are manufacturer claims, not independently normalized measurements across all seven products.

Marvell described customer sampling beginning in the second quarter of 2026, without an equivalent public announcement of production-volume shipments at the time of this comparison. The chip emphasizes a 512-port radix, fewer network hops and flexible electrical or optical packaging. A lower target wattage can reduce the energy needed to move traffic, but power per useful delivered bit also depends on link optics and network utilization.

3. NVIDIA Spectrum-6 — 102.4 Tbps

The NVIDIA Spectrum-6 ASIC powers a new generation of Spectrum-X Ethernet. NVIDIA specifies 102.4 Tbps per chip using 512 × 200G SerDes lanes, with the SN6600 system exposing up to 128 × 800GbE links. Larger systems can contain multiple Spectrum-6 chips: the 409.6-Tbps SN6800 configuration uses four processors and therefore is not a 409.6-Tbps single-chip result.

NVIDIA said in July 2026 that Spectrum-6 switches were arriving in gigascale AI factories, while industry research reported shipments of Spectrum-X co-packaged-optics switches to selected partners. The company’s approach combines the switch, adapters, congestion management and software; the advertised advantage is end-to-end operation for GPU-heavy workloads, rather than raw bandwidth alone.

2. Cisco Silicon One G300 — 102.4 Tbps

Cisco Silicon One G300 supports 102.4 Tbps and designs with 64 × 1.6TbE interfaces. Its architecture includes a large shared buffer and packet scheduling intended to handle bursts in AI training and inference traffic. Cisco unveiled the device in February 2026 and said on October 12 that customer sampling was underway and its first G300-powered systems were already shipping.

Cisco has reported improvements in network utilization and job completion time from its Intelligent Collective Networking technology, but those results depend on workload and test configuration. They cannot establish the G300 as faster than every other 102.4-Tbps chip under all operating conditions. The key commercial marker is the company’s report of G300 systems reaching customers by mid-October.

1. Broadcom Tomahawk 6 — 102.4 Tbps

Broadcom’s Tomahawk 6 takes the first editorial position among the 102.4-Tbps tie because the company confirmed production-volume shipments in March 2026. The chip can support 100G or 200G SerDes and high-density Ethernet links, making a single-ASIC 102.4-Tbps fabric possible in systems that previously required more switch silicon.

Broadcom has also shipped the related TH6-Davisson co-packaged-optics version, an alternative optical arrangement using the same 102.4-Tbps bandwidth class. We count the Tomahawk 6 family once rather than padding the ranking with separate optical-packaging variants. Our earlier OCP technology report explains its role in next-generation AI racks.

Bandwidth Alone Does Not Determine the Best AI Network

The transition from 51.2 to 102.4 Tbps means the maximum advertised switching bandwidth of a single chip has doubled, but that is not the same as doubling a data center’s useful throughput. Congestion, links per accelerator, port speeds, latency, packet loss, optical power, cooling and the network topology can all become bottlenecks. Even within the 102.4-Tbps group, shipping status varies and the available documentation does not provide a single impartial benchmark for all four architectures.

High-capacity switches are central to the design of large AI network racks, co-packaged optical systems and scalable data center infrastructure. A 102.4-Tbps chip that draws one kilowatt of power has a nominal chip-only energy intensity of about 9.77 picojoules per switched bit at maximum rated throughput (1,000 W ÷ 102.4 trillion bits per second). That illustrative arithmetic excludes optics, fans, other system components and any loss from partial utilization. It is not a measured Tomahawk, Cisco, NVIDIA or Marvell result.

The next meaningful comparison will be commercial deployments, power measured at the full system, supported optics and successful handling of real AI traffic—not just another larger number on a product sheet. This ranking reports the best-supported silicon figures as of late October 2026; future chips advertised at 200T or 400T will require their own sampling, delivery and system evidence.

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