Former Apple CPU architect Gerard Williams III says artificial intelligence is already accelerating the development of next-generation processors at his new venture, NUVACORE. In a November 12, 2026, Bloomberg Power On interview with Mark Gurman, Williams described reducing an early CPU performance-modeling process that traditionally takes seven to 12 months to approximately two to three months. The improvement is a company-reported engineering result, not an independently benchmarked speedup or evidence of a completed chip.
Performance modeling explores potential CPU designs before engineers commit to complete physical implementation. Simulations and architectural experiments can compare execution throughput, memory behavior, cache arrangements and power tradeoffs. Williams says AI assists with the exploratory work, leaving engineers more room to test ambitious alternatives. A faster modeling phase does not eliminate verification, physical design, fabrication, packaging or software enablement.
Why an AI Data Center Still Needs a Strong CPU
Graphics processors handle much of the intensive parallel mathematics behind large language models. General-purpose CPUs perform different jobs: scheduling processes, orchestrating system memory, coordinating storage and networking, and managing security and control software around accelerators. Williams argues that better performance per watt in those host processors could improve total data-center efficiency rather than simply chasing higher clock speeds.
NUVACORE’s official WarpCore and Core First description says its clean-sheet architecture targets sustained throughput and efficiency per unit of silicon area. Its engineers are considering foundational microarchitecture before committing to the final instruction-set implementation. Earlier BitcoinVersus.Tech reporting examined WarpCore’s x86, Arm and RISC-V design options. The choices have real implications for software compatibility, verification and intellectual-property licensing, as the Qualcomm–Arm licensing verdict illustrates.
AI-Assisted Design Still Faces the Silicon Test
Williams sees AI models as extensions of specialist engineering teams, not substitutes for experienced CPU architects. Beyond initial simulations, tools may also help teams explore verification scenarios and search for design problems across enormous combinations of internal processor states. Whether those tools consistently find more defects, reduce final verification costs or improve shipped silicon remains to be demonstrated by reproducible results.
He suggested AI could eventually shorten an end-to-end clean-sheet development program, traditionally roughly two and a half to three years, toward a two-year design cycle. The possibility is a forward-looking estimate. NUVACORE has not publicly supplied an independently validated WarpCore performance score, customer deployment or shipping date. The startup has discussed both chiplet integration with accelerators and complete server products as possible outcomes rather than released devices.
From Apple’s A7 to Nuvia and a New Startup
Williams helped lead CPU development at Apple during the transition from the 64-bit A7 generation toward the architectural foundations later used in the M1 family. He left Apple in 2019, before the M1 Mac launch in 2020, so the commercial release should not be characterized as work he supervised at launch. He described collaboration with Apple’s silicon engineering leaders Johny Srouji and John Ternus, emphasizing the contribution of teams rather than a single chip designer.
He later co-founded Nuvia, which Qualcomm acquired for $1.4 billion in March 2021, before going on to create NUVACORE with fellow CPU veterans John Bruno and Ram Srinivasan. Its April 2026 introduction positioned efficient general-purpose cores as a central ingredient in continuously running AI systems. BitcoinVersus.Tech previously covered the company’s reported fundraising ambitions and unresolved commercial milestones, while its Arm architecture explainer outlines the distinction between an instruction set and a physical CPU design.
The stakes are substantial: hyperscalers need host compute that keeps costly AI accelerators fed without turning electrical power, floor space or cooling into the next bottleneck. NUVACORE’s differentiator will depend on measurable throughput, power consumption, chip area, software support and real-world total cost—not pedigree or early simulation speed alone.
BitcoinVersus.Tech Editor’s Note: Bloomberg’s November 12 interview establishes Williams’s statements about engineering methods and planned products. NUVACORE’s public website and April 2026 announcement establish its Core First positioning; Qualcomm’s original acquisition announcement confirms the Nuvia transaction. Reported modeling gains and future design timelines are management claims, not independent production benchmarks. The original cover is an editorial illustration, and its CPU floorplan is conceptual. We volunteer daily to ensure the information on our platform is Verifiably True. Support independent technical journalism with the original 5,000-satoshi donation QR below. Before donating, verify the receiving address 3C9o19EH5HSiwEPyCTmEKzxhNCbo2X6TTb.
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