Siemens has launched Tessent Silicon Executable, a new semiconductor-test tool that can deliver deterministic test patterns through high-speed interfaces such as PCIe and USB.
In its October 13 announcement, Siemens said the software extends its Tessent workflow from design-for-test insertion and pattern generation into direct execution on silicon. The goal is to let the same test content move across automated test equipment, system-level test, bench and in-system environments without repeated pattern conversion.
Teradyne says it has already integrated the software into UltraPort and IG-XL on UltraFLEXplus, allowing Streaming Scan Network content to reach a device through its own PCIe interface. Failure data can then flow back into existing Tessent diagnosis tools.
The change matters as chiplet-based processors grow more complex, PCIe 6 enters AI servers, and new silicon still has to move through bring-up and validation efficiently.
Why it matters: chip testing is becoming a bandwidth problem. Reusing the interfaces already built into a device could reduce test overhead and speed debugging as AI and data-center chips add more cores, chiplets and test data.
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