Qualcomm is trying to change the scoreboard for AI data centers. Instead of asking only how many FLOPS a system can produce, the company is pushing a more operational question: how many useful AI tokens can a rack generate for every watt it consumes?
That was the center of Qualcomm’s AI Infra Summit 2026 presentation, where the company showed its Dragonfly rack-scale platform for agentic AI inference. Dragonfly combines CPUs, inference accelerators, custom silicon, memory architecture, networking, and software into a system designed around sustained inference efficiency rather than peak arithmetic throughput alone.
The shift matters because agentic AI can generate far more inference work than a simple chatbot exchange. Agents reason over longer contexts, call tools, maintain state, retry tasks, and stay active for longer periods. That makes memory movement and power consumption increasingly important to the economics of the rack.
A recent Counterpoint Research X post framed the same problem as the “memory wall”: compute is getting faster, but feeding that compute efficiently is becoming the bottleneck.
Dragonfly Treats Memory as Part of the Compute Engine
Qualcomm’s key architectural bet is High Bandwidth Compute, or HBC. Rather than moving every operation back and forth through conventional memory paths, HBC places compute much closer to memory so some data-intensive work can happen where the data already lives.
That is especially relevant during LLM decode, when the processor repeatedly pulls model weights and context from memory to generate the next token. In that phase, raw compute units can sit underutilized if memory cannot feed them quickly enough.
Independent Counterpoint analysis describes HBC as Qualcomm’s attempt to attack that memory bottleneck by bringing memory and compute closer together while reducing the energy spent moving data.
The concept fits a broader trend BitcoinVersus.Tech has been tracking in memory-first AI inference architectures, where the limiting resource is increasingly the ability to move model data efficiently rather than simply adding more arithmetic units.
Qualcomm Says the Better Metric Is Tokens per Watt
Qualcomm’s published estimates claim Dragonfly can deliver up to eight times better tokens per second per watt than contemporary GPU-based systems on selected models. The company also claims HBC can provide up to six times higher memory bandwidth per watt than conventional HBM-based approaches and far greater memory capacity per watt than SRAM-based designs.
Those figures are Qualcomm estimates, not independent production benchmarks, so the important test will be how Dragonfly performs once customers deploy the hardware at scale. But the choice of metric itself is significant. Tokens per watt directly connects AI output to the data center’s hardest physical constraint: available power.
The data center implication is straightforward. If two racks can deliver the same useful inference throughput but one draws materially less power, the more efficient system can fit more AI capacity behind the same utility connection, switchgear, transformers, UPS systems, and cooling plant.
One Trillion Parameters on a Single AI200 Card
At the summit, Qualcomm demonstrated Kimi K2.5, a one-trillion-parameter model, running on a single Dragonfly AI200 accelerator card. Qualcomm presented the demo as evidence that large memory capacity can reduce how aggressively operators need to split models across many accelerators.
That matters because distributing a model across more devices creates another tax: networking. Every time accelerators have to exchange activations, model state, or intermediate results, the interconnect becomes part of inference latency and power consumption.
BitcoinVersus.Tech recently covered Qualcomm’s work with AWS on custom AI silicon and 1.6T optical connectivity. Dragonfly shows why those pieces belong together. An inference rack is increasingly a coordinated system of compute, memory, networking, cooling, and power rather than a collection of independent chips.
Networking Still Decides Whether the Rack Scales
Memory efficiency can reduce unnecessary traffic, but it does not eliminate the network. Dragonfly includes high-speed connectivity for scale-up and scale-out, reflecting the reality that large inference systems still have to move enormous amounts of data between accelerators, storage, and adjacent racks.
That is why the industry’s move toward 1.6T Ethernet deployment matters alongside new accelerator architectures. Faster optics and better memory efficiency attack different parts of the same bottleneck: keeping expensive compute fed without wasting power.
AI Infrastructure Is Becoming an Efficiency Competition
For years, AI hardware competition was easy to summarize with bigger training clusters and higher peak compute numbers. Inference changes the equation because useful output happens continuously and power is paid continuously.
That makes rack-level efficiency a business and engineering problem at the same time. Better memory utilization can reduce idle compute. Better networking can reduce communication delays. Better software can schedule work more efficiently. Better cooling can reclaim electrical capacity for processors instead of facility overhead.
Qualcomm is betting that this shift creates room for a different kind of accelerator platform. Dragonfly does not have to win a theoretical FLOPS contest if it can prove that a rack produces more useful inference within a fixed power envelope.
The hardware still has to prove those claims in large customer deployments. But the scoreboard is already changing. In the agentic AI era, the winning data center may not be the one with the most compute on paper. It may be the one that turns each megawatt into the most useful work.
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