Quantum Blockchain Technologies has received a U.S. patent for a Bitcoin-mining ASIC technique designed to remove redundant work from the SHA-256 message scheduler. U.S. Patent No. 12,756,574, “Message Scheduling for Cryptographic Hashing,” was issued October 6, 2026, giving QBT an enforceable U.S. right around what it calls ASIC Ultra Boost.

This is different from simply shrinking a miner onto a newer process node. As our recent look at BGIN’s 4 nm BT1 ASIC explained, process technology is only one part of mining-compute performance. QBT is attacking the hashing datapath itself: reuse work that does not change between candidate messages so the circuit can perform fewer operations.

What ASIC Ultra Boost Changes

Bitcoin miners repeatedly run SHA-256 while changing portions of candidate block-header data in search of a valid hash. The patented method identifies partially calculated values associated with portions that remain unchanged, stores those values, then reuses them when processing subsequent messages. The USPTO patent record lists 18 claims covering this cryptographic-hashing approach.

The Silicon Savings Are Small—but Real

QBT says post-synthesis analysis on a reference architecture using the open SkyWater 130 nm process reduced silicon area in the SHA-256 message scheduler by 2.42% and register count by 2.82%. Across the complete SHA-256 pipeline, including scheduler and compressor, the reported reductions were 0.81% in area and 1.16% in registers.

Those percentages should not be confused with a claim that a finished miner will suddenly improve its wall efficiency by the same amount. Real machine efficiency includes the entire ASIC, voltage regulation, control electronics, fans or pumps and other losses—the same distinction behind why nameplate, wall and facility J/TH are different measurements.

Why the Message Scheduler Matters

A SHA-256 engine is not one giant operation. The message scheduler prepares words that feed the compression rounds, and mining ASICs replicate hashing logic many times to maximize parallel work. Saving circuitry inside a repeatedly instantiated block can therefore matter even when the percentage reduction for one block looks modest.

The practical value ultimately depends on the architecture that implements it. QBT says its reference design removes 668 registers per message-scheduler instance, but a commercial ASIC manufacturer would have to integrate the method into its own pipeline, validate timing and physical design, manufacture silicon and prove that the resulting miner produces a worthwhile real-world gain.

Patent Granted Does Not Mean Miner Shipping

That distinction is important. QBT’s October 7 announcement says the company is pursuing licensing and other commercialization arrangements with ASIC manufacturers. It does not announce a mass-produced Ultra Boost miner or independently verified fleet-level efficiency result.

For operators, the proof will eventually appear in familiar metrics: stable TH/s, J/TH, accepted-share rate, silicon yield, thermal behavior and uptime. Our explainer on accepted, rejected and stale mining shares shows why faster theoretical hashing is only useful when the miner reliably turns that work into valid pool submissions.

The Bigger Mining-Compute Race

The patent is another sign that Bitcoin-mining competition is moving deeper into silicon design. Process nodes still matter, but so do scheduler logic, datapath architecture, clocking, voltage, packaging, firmware and system integration. When mature ASICs are already heavily optimized, even relatively small improvements can become interesting if they can be replicated across thousands of hashing engines and millions of machines.

For now, ASIC Ultra Boost should be viewed as patented and measured at the synthesized reference-design level—not as a proven commercial-miner efficiency breakthrough. The next meaningful milestone is licensing or silicon implementation that lets miners compare the technique against shipping SHA-256 hardware.

Editor’s Note: BitcoinVersus.tech reports on Bitcoin mining hardware from semiconductor design through hashboards, firmware, cooling and fleet operations. This article is informational and is not investment advice.