Marvell has introduced second-generation Structera X CXL memory expanders aimed at one of AI infrastructure’s growing bottlenecks: memory capacity.
According to Marvell’s October 12 announcement, the Structera X 3406 and 3506 move to CXL 3.2, PCIe Gen 6 and six DDR memory channels—50% more channels than the previous generation. The 3406 supports up to 9TB of DDR4, while the 3506 supports up to 6TB of DDR5 per controller.
Marvell says the chips can share memory across up to four hosts with as much as 256GB/s of host bandwidth. Its inline LZ4 compression is rated for up to 250GB/s and, depending on workload, can deliver 2–3x more effective capacity. For LLM serving, Marvell claims up to 40–50% faster time to first token at the same context length versus its prior generation. Those figures are vendor benchmarks, not independent measurements.
The launch expands a trend BitcoinVersus.Tech has been tracking through Marvell’s OCP 2026 infrastructure push, PCIe-over-optics rack designs and next-generation HBM4 memory.
Marvell’s Structera product page positions CXL as a way to separate memory scaling from CPU replacement. The new 3406 and 3506 are expected to begin sampling in Q1 2027.
Editor’s Note: Capacity, compression and latency improvements above are Marvell claims and may vary by workload and system design.
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