A server can have fast processors and still run short of usable memory. Compute Express Link (CXL) addresses that imbalance by allowing processors to access memory and accelerators through a cache-coherent connection built on PCI Express. In November 2025, the industry consortium released CXL 4.0; throughout 2026, vendors and researchers have continued testing how memory sharing works under demanding AI workloads.

How pooled memory works

In ordinary servers, DDR5 modules sit close to each CPU. Applications running elsewhere cannot automatically borrow unused capacity. CXL memory expanders add another accessible memory tier; compatible switches and software can also organize capacity into pools for multiple hosts. Think of it as moving beyond each server’s fixed memory allocation, not turning every rack into one unlimited computer.

That distinction matters for memory-centric AI rack designs. Models can require substantial key-value cache storage during inference, and capacity pressure can force data toward slower tiers. CXL may provide additional addressable capacity, but capacity is not equivalent to local DRAM bandwidth or latency.

What changed in CXL 4.0

The CXL 4.0 release doubled the nominal per-lane transfer rate from 64 to 128 GT/s, added bundled-port connectivity and strengthened memory reliability features. GT/s counts transfers, not delivered gigabytes per second; actual usable throughput depends on link width, encoding, protocol overhead and implementation. The consortium says the update preserves compatibility with earlier CXL revisions.

Previous releases laid the groundwork: CXL 2.0 introduced switching and pooling, while 3.x expanded fabric and sharing capabilities. That is why a 9 TB CXL memory expansion platform and Astera Labs’ memory controllers are relevant without automatically supporting every new CXL 4.0 feature. Our PCIe retimer explainer covers another essential signal-integrity component.

The real performance test

Real deployments still face congestion. A 2026 USENIX study investigated competing flows inside switched CXL pools, showing that unmanaged sharing can hurt neighboring applications. Another NSDI 2026 project explored alternative connection layouts for better memory utilization. Neither establishes universal improvements for all data centers.

USENIX NSDI 2026 research presentation on congestion and fairness in switched CXL memory pooling; technical talk, not a vendor product benchmark.

For operators, the question is practical: does pooled capacity reduce stranded memory enough to justify switching hardware, power, firmware and software complexity? The consortium’s August 2026 recap describes working CXL 3.x demonstrations, not proof that 4.0 is already everywhere. Future deployments will be judged by measured workload performance and cost, not the headline link speed alone.

NSDI 2026 researchers explain the Octopus CXL memory-pod design and its experimental results; results are specific to their test conditions.

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