SK hynix is proposing a different way to build AI racks: put memory at the center instead of treating it as capacity permanently attached to individual CPUs and GPUs.

At the 2026 OCP Global Summit, SK hynix Senior Vice President Hoshik Kim presented its Memory-centric AI Rack System, or MARS. In an official SK hynix America update, the company said the architecture uses CXL to connect CPUs and GPUs to a rack-level memory pool and enable zero-copy data sharing.

SK hynix presents the MARS memory-centric rack concept at OCP 2026.

A recent SK hynix community discussion tracks the company’s broader move toward CXL memory pooling and new AI memory tiers.

The idea is to reduce stranded memory. In a processor-centric rack, one server can run short while another has unused capacity. A shared pool lets systems allocate capacity where it is needed without adding another expensive accelerator just to gain more attached memory.

Seoul Economic Daily reports that SK hynix is supporting customized MARS testing with partners. That makes MARS an active architecture program, not evidence of a broadly shipping rack product yet.

SK hynix explains the system-architecture work behind next-generation AI memory.

A second discussion highlights the limits of CXL: it can expand and share capacity, but it does not match HBM bandwidth and is better viewed as a complementary memory tier.

The direction fits a wider shift already visible across the industry. BitcoinVersus.Tech recently covered Marvell’s CXL chips supporting up to 9 TB of memory, Astera Labs’ CXL 3.2 memory platform, and SK hynix’s push beyond HBM.

MARS does not eliminate HBM. Instead, it reflects a growing effort to make memory capacity more shareable and to move less data across the network as AI inference becomes more memory-intensive.

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