China’s ChangXin Memory Technologies is pushing conventional server DRAM toward a much denser cell layout. CXMT President Cao Kanyu says the company plans to introduce a DDR5 RDIMM using a 4F² memory-cell architecture before the end of 2026, according to TrendForce’s reporting on the company’s recent technical presentation.
The number sounds abstract, but the geometry is the story. Conventional DRAM cells are commonly described around a 6F² footprint, where F represents the minimum feature dimension used in the layout. Moving toward 4F² means fitting the same basic storage function into roughly two-thirds of the cell area. In theory, that can produce substantially more memory capacity from the same silicon area. Real chips will not gain a perfect 50% density increase because peripheral circuitry, routing, redundancy and manufacturing margins still consume die space.
CXMT’s proposed design uses what it calls a Vertical Surrounded Gate transistor. Turning the transistor structure vertically can improve electrostatic control as the cell shrinks, while reducing leakage and short-channel effects that become harder to manage at smaller dimensions. The company has also been developing wafer-level hybrid bonding, which could allow memory arrays and peripheral CMOS circuitry to be manufactured separately and then joined with very dense interconnects.
That architecture still has to survive the much less glamorous part of semiconductor engineering: yield, reliability and qualification. A server RDIMM is expected to operate continuously inside systems where memory errors can crash workloads or corrupt data. Vendors have to prove electrical margins, thermal behavior, error handling and long-duration stability across large numbers of modules. CXMT has not publicly disclosed the new module’s capacity, speed bins, manufacturing yield or customer qualification results.
CXMT does have evidence that its broader process technology is moving quickly. In September, the company announced mass production of its fifth-generation DRAM platform, citing an 11.95 nm active-area half-pitch and a 45:1 capacitor aspect ratio. Those specifications do not prove that 4F² server memory is ready for volume deployment, but they show why the new architecture is being taken seriously rather than dismissed as a laboratory-only concept.
The timing matters because memory has become one of the biggest constraints around AI infrastructure. BitcoinVersus.Tech recently explained how HBM feeds modern accelerators, why the HBM boom is also pressuring ordinary DRAM supply, and the basic architectural difference between SRAM and DRAM. Server DDR5 does a different job from HBM, but AI servers need enormous amounts of both.
The competitive question is therefore not simply whether CXMT can fabricate a denser cell. It is whether it can manufacture that cell cheaply, repeatedly and at server-grade reliability while scaling enough wafers to affect global supply. Samsung and SK hynix are also pursuing next-generation cell structures, so an early product announcement does not automatically equal a durable technology lead.
Why it matters: DRAM has spent decades scaling by squeezing more bits from each wafer. If 4F² becomes manufacturable at high yield, it could extend that scaling path at exactly the moment AI systems are consuming unprecedented amounts of memory. CXMT’s year-end target is important—but the decisive milestone will be qualified, high-volume server modules, not the announcement itself.
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