Complementary FET, or CFET, moves CMOS scaling into the third dimension by stacking nMOS and pMOS transistors vertically instead of placing them side by side. Gate-all-around nanosheets improved electrostatic control by wrapping the gate around the channel; CFET takes the next step by using vertical device stacking to reduce the lateral footprint of complementary logic. This lesson follows OSSEC.009: Gate-All-Around Nanosheet Electrostatics.

Elementary Overview

A CMOS logic gate needs both n-type and p-type transistors. Traditionally those devices sit next to each other and consume separate horizontal area. A CFET places one above the other so both transistor types share more of the same footprint. The simplest way to remember the idea is: GAA surrounds the channel; CFET stacks the complementary channels.

Learning Objectives

• Explain why vertically stacking nMOS and pMOS can shrink logic-cell footprint.
• Distinguish conventional side-by-side CMOS from CFET architecture.
• Compare monolithic and sequential CFET integration flows.
• Connect CFET geometry to electrostatics, resistance, capacitance, and thermal behavior.
• Explain why backside power and backside contacts become increasingly valuable in vertically stacked logic.
• Identify alignment, thermal-budget, isolation, contact, and yield challenges.
• Relate current Intel, imec, and IBM research to the broader CFET roadmap.

Why CFET Comes After Gate-All-Around

Gate-all-around nanosheet transistors still place complementary nMOS and pMOS devices beside each other inside a standard cell. As lateral pitches become more difficult to shrink, the unused vertical dimension becomes increasingly valuable. Imec’s logic roadmap identifies CFET as a candidate architecture after nanosheet and forksheet generations because stacking the complementary devices can remove n-to-p separation from the cell-height calculation and enable denser standard cells.

The Density Advantage

A conventional CMOS inverter needs an nMOS device and a pMOS device with routing and isolation between them. In a simplified planar view, the cell must reserve lateral space for both. In a CFET, one device tier is placed above the other, so the horizontal footprint can be reduced even if the individual channel dimensions do not shrink by the same amount. This is a different kind of scaling: density improves by architectural stacking rather than only by making every feature narrower.

That does not mean the area gain is automatically 2×. Contacts, isolation, vertical interconnects, gate access, source/drain routing, power delivery, design rules, and process margins consume real space. CFET benefit must therefore be evaluated at the standard-cell and circuit level, not only from a device cross-section.

Monolithic CFET

Monolithic CFET builds the vertically stacked device structure through one tightly integrated process flow. Imec describes monolithic CFET as a route where stacked silicon/silicon-germanium layers are patterned and processed into top and bottom devices with common vertical integration steps. The attraction is compact alignment and a potentially direct path to high-density stacking. The difficulty is that high-aspect-ratio patterning, selective material removal, conformal deposition, isolation, gate formation, source/drain engineering, and contacts all become more demanding inside one three-dimensional device structure.

Sequential CFET

Sequential CFET builds the lower and upper device tiers more independently. A top semiconductor layer can be transferred or bonded above a completed lower tier, after which the upper transistor is fabricated. This can simplify some device-processing steps because each tier receives more independent patterning, but it introduces its own problems: wafer bonding, front-to-back alignment, thermal-budget limits, vertical interconnect formation, distortion, and the need to protect the lower transistor while the upper transistor is built.

Electrostatics Still Matter

CFET does not replace the need for strong transistor electrostatics. The stacked devices are still expected to use advanced gate-all-around or similarly well-controlled channels. Gate length, channel thickness, dielectric thickness, work function, source/drain geometry, and parasitic fields still determine threshold behavior, DIBL, subthreshold leakage, drive current, and variability. Vertical stacking changes how two complementary devices share space; it does not remove the underlying MOSFET physics learned in earlier lessons.

Parasitic Resistance and Capacitance

The electrical benefit of a dense device can be lost if access resistance and capacitance grow too much. A CFET needs low-resistance contacts to both upper and lower source/drain regions, practical gate contacts, compact vertical connections between complementary devices, and local interconnect that does not erase the area savings. New routing geometries can shorten some paths, but densely stacked conductors can also increase coupling capacitance. Engineers therefore evaluate total circuit delay and energy rather than transistor current alone.

Thermal Budget and Self-Heating

Vertical integration creates a thermal problem in two different ways. First, the upper-device fabrication sequence may expose the lower transistor to later high-temperature steps that can change dopants, interfaces, stress, or gate materials. Second, closely stacked active devices create more difficult heat-removal paths during operation. A process can be electrically excellent at room temperature yet become unattractive if it cannot survive manufacturing temperatures or control self-heating under realistic power density.

Backside Power and Backside Contacts

As device stacks become taller and frontside routing becomes more crowded, power delivery increasingly moves to the backside of the wafer. Backside power can free frontside metal resources for signal routing, while direct backside contacts can provide shorter electrical paths to buried devices. Intel’s recent research combines CFET development with backside power and direct backside contacts, and imec likewise treats advanced contacting and backside connectivity as important CFET enablers.

2026 Research Snapshot

CFET remains a research and development architecture rather than a mainstream production transistor. Intel reported monolithic CFET inverter operation at a 45 nm gate pitch at the 2026 VLSI Symposium, extending its earlier 60 nm stacked-CMOS demonstration. Imec continues developing monolithic and sequential CFET process modules and design-technology co-optimization for future logic nodes. IBM’s NanoStack research uses sequential nanosheet-on-nanosheet stacking and is now being paired with early process-design-kit and manufacturing-model work aimed at preparing an ecosystem for future sub-1-nanometer research.

Engineering Tradeoffs

• Density: vertical nMOS/pMOS stacking can reduce standard-cell footprint.
• Alignment: upper and lower devices, contacts, and vertical interconnects must register with extremely small error.
• Thermal budget: later processing must not damage earlier device tiers.
• Isolation: stacked devices require strong electrical and physical isolation without excessive height.
• Contact resistance: buried terminals must remain electrically accessible.
• Capacitance: close vertical and lateral conductors can increase parasitic coupling.
• Heat removal: stacked active devices can worsen self-heating.
• Variability: mismatch between top and bottom devices can affect inverter balance and timing.
• Yield: a larger number of tightly coupled process modules increases defect sensitivity.
• Design rules: device architecture only delivers value when layouts, routing, and standard cells can use it efficiently.

Engineering Exercise

1. Draw a simplified CMOS inverter with nMOS and pMOS placed side by side.
2. Draw the same logical inverter as a CFET with one transistor tier stacked above the other.
3. Assume the side-by-side layout requires 100 arbitrary area units. If ideal vertical stacking removed 35% of the footprint, calculate the new area.
4. Now add 10 area units for extra contacts and routing overhead. Calculate the practical area and the net percentage reduction versus the original layout.
5. List four process challenges and four electrical parasitics that could prevent ideal CFET scaling.
6. Explain why backside power can become more valuable as frontside routing density increases.

Knowledge Check

1. What does CFET stand for?
2. What two transistor types are vertically stacked in a CFET?
3. Why can CFET reduce standard-cell area?
4. What is the main conceptual difference between monolithic and sequential CFET integration?
5. Why is thermal budget especially important in sequential or vertically integrated devices?
6. Does CFET eliminate short-channel effects?
7. Name three important CFET parasitics or access problems.
8. Why are backside contacts attractive for vertically stacked devices?
9. What did Intel report at the 2026 VLSI Symposium?
10. Why must CFET be evaluated at circuit and standard-cell level rather than from device cross-sections alone?

Answers

1. Complementary field-effect transistor.
2. nMOS and pMOS.
3. It places complementary devices vertically instead of reserving separate horizontal space for each.
4. Monolithic CFET forms the stacked structure in one highly integrated process sequence; sequential CFET builds or transfers device tiers more independently and stacks them through bonding or layer transfer.
5. Later high-temperature processing can alter the already-fabricated lower tier, its interfaces, dopants, stress, or gate materials.
6. No. CFET still relies on strong channel electrostatics, usually with advanced gate-all-around-style devices.
7. Examples include contact resistance, gate resistance, vertical-interconnect resistance, coupling capacitance, source/drain access resistance, and self-heating.
8. They can provide shorter paths to buried devices and reduce frontside routing congestion.
9. Monolithic CFET inverters with vertically stacked nMOS and pMOS devices at a 45 nm gate pitch.
10. Real density and performance depend on routing, contacts, power delivery, parasitics, design rules, thermal behavior, and yield—not only the ideal transistor footprint.

Previous Related Lessons

• OSSEC.009: Gate-All-Around Nanosheet Electrostatics
• OSSEC.008: FinFET Electrostatics
• OSSEC.007: Short-Channel MOSFET Effects

Primary References

• imec — Scaling Monolithic CFET Across Multiple Logic Technology Nodes
• imec — Towards a Process Flow for Monolithic CFET Transistor Architectures
• Intel Foundry — 2026 VLSI CFET Research Update
• IBM Research — NanoStack Transistor Architecture for CMOS 7A Node and Beyond
• IBM Research — Preparing Chip Designers for the NanoStack Era

Rotation next: Robotics Technician.

BitcoinVersus.Tech Editor’s Note:
We volunteer daily to ensure the credibility of the information on this platform is Verifiably True. If you would like to support to help further secure the integrity of our research initiatives, please donate using the QR code provided

For best QR-code scanning results, please scan this donation code from a desktop or larger screen. Mobile screens may prevent camera recognition.

BitcoinVersus.Tech provides technical education and analysis for informational purposes only.