AMD’s ROCm software stack has now been demonstrated with a RISC-V server acting as the host for GPU-accelerated AI inference. SiFive and AMD showed ROCm 10.0 running on SiFive’s BigSky SF-2U870 datacenter development platform, where 32 SiFive P870-D CPU cores controlled an AMD Radeon AI PRO R9700 GPU running a Gemma4-E2B language model.
The September 15 demonstration matters because the host processor was not x86 or Arm. It was RISC-V. A SemiWiki technical post published September 30 highlighted the same division of labor: the P870-D CPUs operated the server while the Radeon accelerator handled inference through ROCm.
According to SiFive’s announcement, the system is explicitly a demonstration platform rather than a claim that ROCm on RISC-V is already a broadly supported production configuration. The companies said they will continue evaluating optimization of ROCm on RISC-V servers, with the goal of supporting faster processing, additional acceleration use cases and larger models.
RISC-V becomes the host, not the accelerator
The architectural distinction is important. The SiFive CPU is not replacing the GPU’s matrix engines. Instead, RISC-V is taking the role normally occupied by a server-class x86 or Arm host: booting the system, running the operating environment, coordinating software and feeding work to a discrete accelerator over PCIe.
In the demonstrated configuration, AMD’s Radeon AI PRO R9700 performs the inference offload while the P870-D complex operates as the head node. That separates the instruction-set question from the accelerator question. A datacenter can theoretically choose a RISC-V host architecture while retaining a GPU programming stack built around ROCm.
This is one reason open instruction sets are becoming relevant above the embedded tier. BitcoinVersus.tech’s instruction-set architecture guide explains that the ISA defines the software-visible interface between programs and the processor. Moving RISC-V into a server host role therefore depends as much on software enablement as on raw CPU core performance.
BigSky is built as a software-porting machine
SiFive’s BigSky SF-2U870 is designed for software porting, workload tuning and validation rather than as a conventional volume server product. The machine uses 32 P870-D cores running at 2.0 GHz, 256 GB of DDR5-5600 memory, four PCIe Gen5 x16 interfaces providing 64 Gen5 lanes, two 7.68 TB U.2 NVMe SSDs and a 10/25 Gb OCP 3.0 network interface.
Those PCIe lanes are especially important for accelerator work. A RISC-V server cannot become a useful AI host simply by executing Linux; it also needs enough I/O bandwidth and a mature software path to attach GPUs, storage and networking devices expected in modern datacenter systems.
Embedded Computing Design independently reported the same Gemma4-E2B setup and BigSky hardware configuration, describing the collaboration as an effort to combine AMD’s open-source GPU software ecosystem with the RISC-V architecture for datacenter AI.
ROCm is the bridge to the GPU
ROCm is AMD’s open-source software platform for GPU computing. In this demonstration, its significance is less about introducing a new accelerator and more about proving that the software path can cross an ISA boundary at the host.
That makes this a software-ecosystem milestone rather than a benchmark victory. SiFive and AMD did not publish evidence that the RISC-V host outperforms an equivalent x86 or Arm host, and the demonstration should not be interpreted that way. What it establishes is that the stack can run an AI model with a RISC-V CPU complex coordinating an AMD GPU.
The distinction also separates this work from BitcoinVersus.tech’s recent coverage of DeepSeek and Huawei opening an Ascend AI programming stack. Both developments concern software access to accelerators, but the SiFive/AMD work focuses on changing the host ISA beneath an existing GPU ecosystem.
RISC-V is climbing into larger systems
RISC-V’s historical strength has been configurability across microcontrollers, embedded systems and specialized silicon. Datacenter adoption raises a different set of requirements: server-class memory, PCIe, storage, networking, virtualization, operating systems, compilers, libraries and accelerator support all have to arrive together.
That ecosystem challenge is why a development server can matter even before broad commercial deployment. Software vendors need physical systems on which to port code, expose assumptions tied to x86 or Arm, validate drivers and tune workloads. BigSky gives that work a rack-mount target rather than limiting RISC-V datacenter development to simulation or smaller boards.
BitcoinVersus.tech recently covered MIPS and Xcelsa using AI to optimize RISC-V custom silicon, another example of the architecture expanding beyond a single fixed processor design. SiFive’s BigSky demonstration attacks the problem from the software side: make a high-performance RISC-V host usable with an established accelerator stack.
Open CPU ISA meets open GPU software
The combination is notable because the two layers are open in different ways. RISC-V provides an open-standard instruction-set architecture from which vendors can build processor implementations. ROCm provides an open-source software environment for programming AMD accelerators. Neither eliminates proprietary hardware, but together they reduce the requirement that an AI server’s host and accelerator software be tied to one traditional CPU ecosystem.
There is still substantial work between a conference demonstration and production datacenter deployment. Driver maturity, performance tuning, enterprise Linux support, virtualization, management tooling and long-term platform validation all matter. SiFive and AMD themselves describe this as an early step.
But the architecture is now concrete enough to run a modern language model: RISC-V CPU cores at the head node, PCIe connecting the system, AMD GPU silicon executing inference, and ROCm supplying the accelerator software layer. That is a much more consequential test for server RISC-V than merely booting Linux.
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