MIPS and Xcelsa Labs are applying artificial intelligence to a difficult semiconductor problem: optimizing production-scale processor logic quickly while proving that the rewritten design remains functionally equivalent to the reference.

AI moves into custom-silicon optimization

The companies announced a strategic, non-exclusive partnership on September 29 combining MIPS’ workload-focused RISC-V platforms with Xcelsa’s Apex design-optimization system. The technical announcement says Apex uses verified and physical-intelligence stacks to explore design alternatives while targeting improvements in power, performance and area.

The companies disclosed one production-scale example. Apex closed a timing-violating critical path in a MIPS load-store unit in under three hours and reduced that path’s delay by 33%. The rewritten block was formally proven equivalent to the reference design. MIPS estimates that a comparable manual workflow would have required roughly one engineer-month. That time comparison is a company estimate, not an independent benchmark.

A related X post from Xcelsa investor Shomik Ghosh highlighted the customer announcement and Xcelsa’s work with GlobalFoundries.

Formal equivalence is the guardrail

Faster optimization matters only if the resulting logic remains correct. Formal equivalence checking mathematically compares the optimized implementation with its reference. Xcelsa’s pitch is therefore not simply that AI can rewrite a design quickly, but that the workflow can optimize it while preserving intended functionality.

That matters as custom AI silicon expands. BitcoinVersus.Tech recently covered OpenAI’s internal custom AI silicon effort and SEMIFIVE’s $52 million U.S. AI accelerator contract, two examples of workloads pushing hardware toward greater specialization.

MIPS builds around RISC-V and Physical AI

MIPS now operates as MIPS by GF under GlobalFoundries and bases its current processor portfolio on the open RISC-V instruction-set architecture. RISC-V International’s recent discussion with MIPS CEO Sameer Wasson explains how an open ISA can give designers a standards-based software foundation while allowing workload-specific hardware customization.

The following English-language EE Times interview with MIPS CEO Sameer Wasson and CTO Yankin Tanurhan explains the company’s software-to-silicon strategy and its focus on Physical AI.

Software starts influencing silicon earlier

Workload-focused silicon reverses the old assumption that hardware must be finalized before software optimization begins. Engineers can profile workloads, explore processor resources around those requirements and validate architecture choices before committing to silicon.

MIPS’ Computex presentation provides a second English-language view of that software-first approach.

BitcoinVersus.Tech’s coverage of Axelera’s 629-TOPS, 45-watt Europa accelerator illustrates why specialization matters at the edge, where latency, power and form-factor constraints can make workload-specific optimization valuable.

The milestone is production-scale iteration

The disclosed 33% critical-path improvement is promising but narrow. MIPS and Xcelsa have not published a broad independent benchmark showing equivalent gains across complete chips or multiple customer designs. The notable development is that AI-assisted optimization is being applied to production-scale processor logic with formal equivalence built into the workflow.

If that approach scales, the semiconductor industry’s use of AI could move beyond coding assistance toward faster hardware-software co-design, with engineers using automated optimization to explore more implementations before a design is committed to manufacturing.

BitcoinVersus.Tech

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