SEMIFIVE and Mobilint are developing a custom AI chip for robots that need to keep processing vision and sensor data even when cloud connectivity is weak or unavailable.
In its October 1 announcement, SEMIFIVE said the chip will combine LPDDR6 memory, PCIe Gen6 and UCIe-S chiplet connectivity under South Korea’s K-On-Device AI Semiconductor program. The target applications include agricultural robots working outdoors, where constant network access cannot be assumed.
The robot is supposed to keep thinking when the network disappears
The most interesting part of the project is not a single benchmark number. It is the architecture goal: move enough AI compute, memory bandwidth and sensor processing onto the machine itself that the robot can continue operating without sending every decision back to a distant server.
IN Electronics independently reports that the project is aimed at real-time on-device robotics processing and that SEMIFIVE will take Mobilint’s performance targets through detailed design, packaging, testing and production.
That approach lines up with a broader shift toward edge and physical AI. BitcoinVersus recently covered Seeed Studio’s fanless industrial edge-AI computer, another system designed to keep inference physically close to cameras, sensors and machines instead of depending entirely on the cloud.
LPDDR6 is there to feed the AI engine
Robotics inference is increasingly limited by how quickly sensor data and model weights can move through the system. LPDDR6 gives the design a path toward higher memory bandwidth while staying focused on lower-power operation than conventional server memory.
That matters for mobile robots because every watt has to come from the machine’s battery or onboard power system. Moving more data without blowing the power budget is part of what separates a deployable autonomous system from a lab demo.
BitcoinVersus has followed the same power-efficiency problem through Ambarella’s X7 physical-AI processor operating in the 2-to-5-watt range, where the design goal is also to put useful AI capability directly inside real-world machines.
PCIe Gen6 and UCIe-S make the package more modular
PCIe Gen6 gives the chip a high-speed path to external accelerators and devices, while UCIe-S is aimed inside the package, connecting function-specific chiplets so they can behave like one integrated processor.
That modularity matters because robotics workloads are heterogeneous. A future robot may need separate blocks for vision, motion planning, control, safety, communications and general-purpose processing. Chiplets give designers another way to assemble those functions without forcing every subsystem into one giant monolithic die.
BitcoinVersus recently covered Intel’s use of UCIe-S across a 16-chiplet Diamond Rapids architecture. The SEMIFIVE/Mobilint project brings the same open chiplet idea into a much smaller physical-AI setting.
Why UCIe is useful for robotics AI
The UCIe Consortium’s own technical overview explains how the standard gives chip designers a common high-bandwidth, low-latency die-to-die interface inside one package. That can make it easier to mix specialized compute blocks while maintaining a standardized interconnect.
SEMIFIVE is taking the chip from specification to production
The project also highlights how custom silicon development is changing. SEMIFIVE says Mobilint can hand over its performance targets early in the process, while SEMIFIVE handles detailed design, implementation, packaging, testing and the path to mass production.
That model lowers the amount of semiconductor-design infrastructure an AI startup has to own internally. Instead of building every downstream design and manufacturing capability itself, Mobilint can focus on the NPU architecture and robotics requirements while a turnkey ASIC partner carries more of the physical implementation.
The result could be a more specialized robotics processor than a repurposed datacenter accelerator. For agricultural machines, drones and autonomous equipment, that specialization can matter more than raw peak compute because latency, power, sensor I/O and network independence all have to work together.
Physical AI is pushing semiconductor design out into the field
This project is another sign that the next wave of AI silicon is not limited to GPUs in racks. Robots operating in fields, warehouses, factories and remote infrastructure need chips that can process the physical world locally, tolerate inconsistent connectivity and fit inside strict power envelopes.
That puts memory, chiplet interconnects and packaging on the same design sheet as neural-network performance. The robot still has to see, decide and move when the network bars disappear.
BitcoinVersus.Tech
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