Astera Labs Leo X-Series Speeds AI Memory With CXL 3.2

Astera Labs Leo X-Series Smart Memory Controller with Scorpio fabric, GPU racks, CXL 3.2 and PCIe 6

Astera Labs has expanded its Leo Smart Memory Controller family with three new products aimed at one of AI infrastructure’s fastest-growing bottlenecks: moving and expanding memory around GPUs and CPUs without forcing every workload to live inside local accelerator memory.

In a new hardware announcement, the company introduced the Leo X-Series plus Leo 2 E-Series and P-Series. The chips extend memory connectivity across fabric-attached GPU memory, CPU-attached expansion, pooling and sharing.

Leo X-Series targets the AI KV cache bottleneck

Long-context and agentic AI workloads can create large KV caches that consume valuable GPU memory. Leo X-Series is designed to attach an additional memory tier to the compute fabric and pair it with Astera Labs’ Scorpio X-Series fabric switches.

Astera Labs reports that its platform-specific Leo X-Series configuration can deliver up to 62% faster time to first token and up to 22% more tokens per second. Those are company-reported workload results, not universal performance guarantees, and actual gains will depend on model, platform and memory topology.

The design illustrates how AI performance increasingly depends on infrastructure surrounding the accelerator, a theme also visible in BitcoinVersus.tech coverage of Qualcomm and AWS custom AI silicon and Axelera’s Europa accelerator.

The English-language AI Infra Summit demonstration above shows Astera Labs presenting the new Leo family, including fabric-attached memory, Scorpio integration and the CXL PCIe 6 E-Series and P-Series configurations.

PCIe 6 and CXL 3.2 expand CPU memory

Leo 2 E-Series and P-Series support PCIe 6 connectivity and CXL 3.2. Astera says the generation doubles memory bandwidth and capacity compared with the previous Leo generation and supports both DDR4 and DDR5 expansion.

The company is also pitching DDR4 reuse as an infrastructure-efficiency tool. Instead of discarding large fleets of deployed memory while DDR5 supply remains tight, hyperscale operators could potentially redeploy qualified DDR4 capacity behind new memory controllers. The reliability layer includes memory-health management, on-chip hardware engines and automated repair.

That system-level approach complements the semiconductor scaling discussed in BitcoinVersus.tech reporting on High-NA EUV chip production, onsemi’s denser AI-rack power devices and Synopsys and TSMC’s A14 design work.

In a technical public update, the brand has also highlighted why agentic workloads can encounter memory limits before compute limits and how CXL over PCIe 6 can expand memory in AI systems.

Scorpio turns memory into part of the fabric

Leo X-Series is designed to work alongside Astera’s Scorpio 320-lane fabric switches. Instead of treating memory only as capacity attached directly to a CPU or GPU, the architecture makes additional memory a resource reachable through the rack-scale fabric.

This is increasingly important as rack-scale GPU systems become larger and the supporting network, power, cooling and memory systems determine how effectively expensive accelerators can be used.

Sampling now, not yet a universal deployment

Astera says the expanded Leo family is sampling with hyperscale customers and was demonstrated at AI Infra Summit 2026 in Santa Clara. Sampling and design wins are meaningful development milestones, but they should not be confused with broad production deployment across the industry.

Independent event coverage confirms that Astera demonstrated Leo X-Series direct fabric-attached memory and Leo 2 CXL PCIe 6 configurations at the summit.

For AI operators, the larger engineering story is straightforward: adding GPUs alone does not eliminate inference bottlenecks. Memory capacity, bandwidth, fabrics, electrical power and cooling increasingly have to scale together.


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6 responses to “Astera Labs Leo X-Series Speeds AI Memory With CXL 3.2”

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