Artificial intelligence is pushing chipmakers toward a new kind of scaling problem: not simply making features smaller, but controlling materials so precisely that a few atoms can change how a transistor behaves.

In an October 6, 2026 technology essay, ASM argued that advanced logic is moving into an era where transistors, materials, and three-dimensional device structures have to be engineered with near-atomic precision. The company’s central point is simple: as AI demands more compute without a proportional rise in power, tiny variations inside the chip matter more than ever.

Why AI Changes the Scaling Problem

For decades, semiconductor progress was often summarized as making transistors smaller. That is still part of the story, but leading-edge devices now depend on increasingly complex structures, new materials, and tighter process control across every 300 mm wafer.

ASM says the 2025 production ramp of gate-all-around, or GAA, transistors established the architecture as a foundation for future logic generations. GAA devices wrap the gate around the channel more completely than a FinFET, giving engineers stronger electrostatic control as dimensions shrink. BitcoinVersus.Tech has already seen the same architecture reach specialized hardware through Samsung 3 nm GAA silicon found inside a WhatsMiner ASIC.

Semiconductor Engineering describes modern GAA devices as stacked nanosheet or nanoribbon channels surrounded by the gate. That geometry improves control, but it also makes fabrication harder because deposition, etching, spacers, gate dielectrics, metals, and buried interfaces all have to be controlled inside tiny three-dimensional spaces.

The Next Step Is CFET

ASM expects GAA to evolve toward complementary field-effect transistor, or CFET, architectures. Instead of keeping N-type and P-type devices beside one another, CFET concepts stack them vertically. That can increase transistor density without relying entirely on another horizontal shrink.

The tradeoff is even more process complexity. Vertical transistor stacking adds new alignment, contact, thermal, deposition, and interconnect challenges. This is one reason leading-edge scaling is increasingly a materials-engineering problem as much as a lithography problem.

Atomic Layer Deposition Becomes More Important

One of the technologies ASM highlights is atomic layer deposition, or ALD. On its ALD technology page, ASM describes ALD as a surface-controlled process that builds ultrathin films through repeated cycles of precursor exposure, purge, reactant exposure, and another purge.

The key feature is that the surface reactions are self-limiting. Once available reaction sites are occupied, that step effectively stops, so repeating the cycle gives engineers extremely fine thickness control. This makes ALD useful for conformal films that have to coat complex three-dimensional structures rather than only flat surfaces.

That process also depends on the rest of the fab working correctly. Stable vacuum systems, controlled gas delivery systems, contamination control inside the semiconductor cleanroom, and reliable wafer handling all affect whether a precision film can be deposited consistently across production wafers.

A Few Angstroms Can Change the Device

ASM’s argument becomes especially clear around the transistor gate stack. Future devices need carefully engineered channel materials, source/drain regions, high-k dielectrics, dipoles, contacts, spacers, and gap-fill films. Those layers interact with familiar electrical concepts such as threshold voltage and the operating behavior of a MOSFET.

At this scale, a film that is slightly too thick, too thin, contaminated, nonuniform, or poorly matched to the underlying substrate can shift electrical behavior. Across a chip containing enormous numbers of devices, that variability can become a performance, power, reliability, or wafer-yield problem.

This Does Not Mean Lithography Stops Mattering

Atomic-scale materials control does not replace lithography. The two have to work together. High-NA EUV photomasks, patterning, etch, deposition, metrology, cleaning, and process integration all contribute to whether the final device can be manufactured at high volume.

What is changing is the balance. Shrinking the printed pattern alone is no longer enough. Engineers increasingly have to co-optimize geometry, chemistry, materials, interfaces, contacts, power delivery, and three-dimensional architecture. That is also why companies such as Applied Materials and Intel are expanding joint development around next-generation transistors, interconnects, and AI-chip packaging.

Packaging Adds Another Materials Problem

The same pressure continues after the wafer is fabricated. Modern AI accelerators increasingly depend on semiconductor packaging, chiplets, interposers, dense interconnects, and advanced substrates to move data and power between compute and memory. The recent shortage of specialized glass cloth used in AI-chip substrates is another reminder that materials far beyond the transistor itself can become system-level bottlenecks.

The Bigger Story Is Performance Per Atom

AI is forcing the semiconductor industry to chase more computation under severe power, thermal, cost, and manufacturing constraints. That makes every layer of the device stack more valuable. A transistor architecture can be elegant on paper, but it still has to survive real-world deposition, etching, cleaning, metrology, wafer handling, and high-volume manufacturing.

ASM’s October 6 message is therefore less about one machine than about the direction of the industry. The next era of chip scaling will still use better lithography and smaller dimensions, but it will increasingly be decided by whether fabs can place the right material in the right place, at the right thickness, across billions of structures with almost no room for error.

The AI race is becoming an atomic-precision manufacturing race.

BitcoinVersus.Tech

Editor’s Note

ASM’s October 6 article is a vendor-authored technology perspective. BitcoinVersus.Tech cross-checked its GAA description against Semiconductor Engineering and linked ASM’s ALD technical material directly so readers can separate the company’s outlook from the underlying process explanation.

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