Bitcoin ASIC Architecture: Bitmain, Canaan, MicroBT & Bitdeer

Bitcoin mining has evolved from general-purpose CPUs and GPUs into one of the most specialized forms of computing in the world.

At the center of every modern miner is an application-specific integrated circuit (ASIC) engineered almost exclusively to execute Bitcoin’s SHA-256 proof-of-work calculations at enormous scale.

Companies such as Bitmain, Canaan, MicroBT, and Bitdeer now compete at the semiconductor level, where improvements in process nodes, voltage management, thermal design, hashing density, and joules per terahash directly determine the computational productivity of an entire mining system.

Understanding these chips therefore provides a foundation for understanding how Bitcoin mining hardware continues to become faster, denser, and more energy efficient.

Bitmain — BM13xx ASIC Architecture

Bitmain’s modern Bitcoin mining architecture is built around its proprietary BM13xx family of SHA-256 ASICs, with successive generations such as the BM1366, BM1368, BM1370 and related derivatives powering the Antminer S19 and S21 generations.

At the silicon level, these chips are not general-purpose processors: most of the die is dedicated to highly parallel SHA-256 hashing pipelines designed to repeatedly perform Bitcoin’s double-SHA-256 proof-of-work calculation with extremely little overhead.

Dozens or hundreds of ASICs are distributed across the miner’s hashboards, receiving work from the control board and processing enormous nonce ranges in parallel. Bitmain’s architectural progression has focused on shrinking switching losses, improving voltage/frequency behavior, increasing hashing density and extracting more hashes from each joule.

That progression is visible at the system level: the original S21 delivers about 200 TH/s at 17.5 J/TH, while the S21 XP reaches approximately 270 TH/s at 13.5 J/TH.

Canaan — Avalon ASIC Architecture

Canaan, the company behind the AvalonMiner platform and one of the earliest commercial Bitcoin ASIC manufacturers, follows essentially the same fundamental computational model but with its own proprietary SHA-256 silicon, hashboard designs and firmware-level tuning. Avalon ASICs contain large arrays of specialized hashing logic rather than CPU-style execution cores; mining jobs are distributed from the miner controller through the hashboards and then divided among many physical ASIC chips operating simultaneously.

Canaan has historically emphasized relatively robust thermal and electrical operation, while newer Avalon generations have increasingly targeted Bitmain-class efficiency through improved silicon and operating-point optimization. Its current A16 generation illustrates that progression: the Avalon A16 produces roughly 282 TH/s at 13.8 J/TH, while the A16XP reaches approximately 300 TH/s at 12.8 J/TH. Canaan does not publicly expose enough transistor-level detail to responsibly describe the exact internal hashing-core arrangement, so the safest architectural description is a highly parallel, fixed-function SHA-256 compute array optimized around voltage, frequency and thermal efficiency.

MicroBT — WhatsMiner ASIC Architecture

MicroBT’s WhatsMiner architecture is the other major mature implementation of industrial Bitcoin SHA-256 computing.

Like Bitmain, MicroBT uses proprietary ASIC silicon mounted across high-current hashboards, with a separate controller supplying block-header work, target information and nonce-search assignments to a large population of parallel hashing engines.

Each ASIC repeatedly executes the SHA-256 compression operations required for Bitcoin mining while the board-level architecture concentrates on delivering extremely stable low-voltage power to the chips and removing several kilowatts of resulting heat.

MicroBT is particularly notable for treating the ASIC, power supply, firmware and cooling system as one tightly optimized compute platform; its air, hydro and immersion WhatsMiner families therefore represent variations of essentially the same specialized SHA-256 computational architecture operated at different electrical and thermal envelopes.

MicroBT publishes miner-level performance much more readily than detailed die-level diagrams, so claims about its exact internal pipeline or core count should be treated cautiously unless supported by semiconductor analysis.

Bitdeer — SEAL ASIC Architecture

Bitdeer is the newest major entrant of these four and arguably the most interesting architecturally because it has publicly discussed its silicon roadmap in unusual detail. Its first proprietary chip, SEAL01, was manufactured on a 4 nm process and demonstrated approximately 18.1 J/TH at the chip level before being integrated into the SEALMINER A1.

The subsequent SEAL02 substantially lowered that figure, with early silicon demonstrating approximately 13.5 J/TH under low-voltage operation and powering the SEALMINER A2 generation. Bitdeer’s longer-term architecture is especially important: the company has described SEAL04 as a full redesign using new digital circuit architectures, rather than simply another process shrink, targeting roughly 5 J/TH at the chip level.

That means Bitdeer is explicitly attacking Bitcoin mining efficiency through both semiconductor fabrication and changes to the underlying digital implementation of the SHA-256 compute engine.

If successful, this represents the same broader architectural trend visible across Bitcoin ASIC development: increasingly dense parallel hashing engines, reduced switching energy, lower operating voltage and increasingly sophisticated chip-level power optimization.

AxeOS, Bitaxe and Proto: Open-Source Bitcoin Mining Hardware

AxeOS represents the software side of the Bitaxe open-source mining ecosystem, but it is important to distinguish open-source system design from open-source ASIC silicon. Bitaxe essentially takes proprietary Bitmain BM-series ASIC chips—including the BM1397, BM1366, BM1368 and BM1370 originally developed for Antminer platforms—and builds an independently designed, fully documented miner around them. Its ESP32-based ESP-Miner firmware includes the AxeOS dashboard, while the PCB schematics, manufacturing files and supporting hardware are publicly available.

In that sense, Bitaxe can be viewed as an open-source branch of the Bitmain hardware ecosystem: the underlying SHA-256 chip remains Bitmain intellectual property, but developers have reverse-engineered enough of its interfaces to place individual Bitmain ASICs into completely new open hardware.

The other major movement toward a more open Bitcoin-mining silicon ecosystem is Block’s Proto, which has developed its own 3 nm mining ASIC and explicitly plans to sell chips independently to third-party hardware builders while making its mining technology open-source where possible.

Proto therefore goes a step beyond Bitaxe: rather than simply opening the board and firmware surrounding somebody else’s ASIC, Block is attempting to open access to the ASIC supply layer itself, alongside modular mining hardware, development kits and open-source fleet-management software.

BitcoinVersus.Tech Editor’s Note:

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6 responses to “Bitcoin ASIC Architecture: Bitmain, Canaan, MicroBT & Bitdeer”

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